10. CACHE Instructions
10.17 Index Load Data (I)
Index Load Data (I) loads a single instruction from the primary instruction cache into the CP0 TagHi, TagLo, and ECC registers. A predecoded instruction in R10000 is 36 bits of data and one bit of parity. The address of the target instruction is VA[13:2] of the CACHE instruction. The way of the target instruction is VA[0] of the CACHE instruction. The instruction itself is loaded into CP0 TagHi[3:0] and TagLo[31:0]. The parity bit is loaded into CP0 ECC[0]. The tag field is not read.
Parity checking is suppressed during operation of Index Load Data (I).
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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